1. Field of the Invention
The invention relates to planarizing techniques for the manufacture of integrated circuits.
2. Description of the Related Art
In a typical integrated circuit device, numerous electronic circuits are fabricated on individual silicon substrates, with the components of individual active devices on the circuit separated by layers of insulation and interconnected by conductive layers. A typical transistor utilized in an integrated circuit device is shown in FIG. 1. Briefly, transistor 10 is manufactured by first providing a silicon substrate 12, shown in FIG. 1 as a P-type substrate, on which insulation layers 14 are grown. Insulation layer 14 may be composed of silicon oxide which is grown by conventional oxidation techniques. Insulation layer 14 is grown to cover the entire surface of substrate 12 and is thereafter patterned to provide the requisite schematic structure of the circuit desired.
As shown in FIG. 2, such patterning usually involves: placing a photosensitive layer or "photoresist" layer 15 over insulation layer 14; placing a preformed mask 17 over the photoresist layer 15; exposing the photoresist layer 15 to a light source; developing the photoresist layer to remove those portions of the layer which have been exposed to the light source (or those portions not exposed, depending on the type of photoresist used); and finally etching insulating layer 14 to form through-holes 18 therein. The structure is then doped to provide n-type impurities through openings 18 to substrate 12 forming the source and drain regions 16 for transistor 10. Subsequently, interconnect layers 20, generally formed of a metal or metal alloy, are deposited on the structure to couple the various components of transistor 10 to other components of the integrated circuit. The resulting upper surfaces 30 of transistor 10, and other transistors formed on the substrate define the topography.
Complex integrated circuits, manufactured to include highly dense concentrations of electronic components, require that additional photolithographic masking resist layers be applied to the surface of insulating layer 14. Generally, such additional layers are required to compensate for physical and chemical limitations of masking materials and lithography equipment available. The advancement of circuit schematics to the Very Large Scale Integration (VLSI) levels (between 100,000-1,000,000 components per chip) has required the addition of even more layers to the wafer surface. These additional masking layers have in turn required more production steps involving the wafer surface, making the resolution of small image sizes more difficult due to light reflection and the thinning of resist layers over the steps.
In the development of such high density manufacturing processes, creating and preserving distinctions in device topography in the latter stages of the device manufacturing process has been the main problem of integrated circuit lithographers. Surface topography presents an image definition problem when the mask image is to be exposed to the structural substrate. For example, contrast effects, photoresist light scattering, and substrate reflectivity all contribute to distortions in the pattern transmitted to the substrate surface during the photolithographic step. These factors have contributed to the dilemma for printing submicron device geometries having a narrow depth of focus (on the order of 0.1 .mu.m).
The general solution to these problems, including the techniques of multilayer resist processing, planarizing layers and reflow, are referred to as "planarizing techniques". Their objective is to achieve a suitable flat surface to allow for the best image definition by the projection lens on the exposed structure.
One solution to this problem, generally referred to as a bi-layer planarizing technique and shown in FIGS. 3A-3E, utilizes two layers of photoresist to resolve small geometries on wafers with varied topographies. Typically, the two organic layers used--the bottom or "planarizing" layer 32 and a top, imaging resist definition layer 34--have different chemistries. A substrate surface 12, having a particular device topography 35 formed thereon, is shown in FIG. 3A. First, as shown in FIG. 3B, a relatively thick layer of resist 32--typically about 1.5 to 4 times the highest step height on the wafer, depending on the resist--is applied and baked to its thermal flow point. Suitable resists for such applications generally are sensitive to deep ultraviolet radiation and include positive-acting polymethylmethacrylate (PMMA). Subsequently, as shown in FIG. 3C, a thin layer of photoresist, sensitive to only near ultraviolet radiation is spun on top of the bottom layer 32 and processed through the development step of the production process (FIG. 3D). In this manner, the photoresist acts as a mask for the underlying planarizing layer. As discussed above, assuming layer 34 is a positive photoresist, the development steps comprise exposing layer 34 through a mask with ultraviolet radiation to transfer the mask pattern to layer 34 and then developing layer 34 to form holes 38 in the thin or "conformal" layer 34 (FIG. 3D). Conformal layer 34 allows transfer of the mask pattern to the wafer surface without such effects as reflections seen in thick wafer surfaces. Layer 32 is then provided with deep ultraviolet radiation exposure through the now-formed holes 38, transferring the pattern directly to the wafer surface. A second development step completes hole resolution, and the wafer is ready for etch. The wafer is thereafter etched, and the pattern provided through to the wafer surface (FIG. 3E).
Unfortunately, many of the planarizing film compositions, such as PMMA or polyimides, must be sufficiently different from the imaging resist to avoid interfacial mixing. Further, imaging through the planarizing layer requires a wavelength different from that for the imaging definition layer. These factors conspire to limit the planarizing compositions to materials that are much more difficult to process than conventional resist systems. Due to their associated high defect levels and processing complexity, bi-layer systems are used only for limited low volume applications.
Limitations in the bi-layer process have led to developments in tri-layer techniques, with materials that were already familiar to the IC manufacturing process. Tri-layer resist processes incorporate a "hard" layer between the two resist layers of the bi-layer process. This hard layer may be a deposited layer of silicon dioxide or other developer-resistant material. In a typical tri-layer process, shown in FIGS. 4A-4F, the first resist layer 42 is applied relatively thickly over the wafer topography, and heated or `baked` to cause a slight flow. Subsequently, the "hard" layer 43 is deposited (FIG. 4B) and a thin top layer of resist 44 is applied (FIG. 4C). The pattern image is formed in the top photoresist layer 44 (FIG. 4D), and subsequently etched via holes 48 in the hard layer 43 (FIG. 4E). The first resist layer 42 (FIG. 4F) and the surface topography are then etched to form the requisite pattern in the device topography (FIG. 4G).
A typical hard planarizing layer used is a spin-on-glass (SOG) layer, the "glass" being a mixture of silicon dioxide in a solvent that evaporates quickly. After spin application, the glass film is heated to leave a planarized, silicon dioxide film.
While the tri-layer techniques, and specifically the SOG process, eliminated many of the shortcomings of the bi-layer technique, use of the SOG layer is fraught with its own complications. For example, the relatively rapid evaporation of the isopropyl alcohol solvent (IPA) can reduce the stability and shelf-life of the silicon dioxide-IPA mixture.
An especially significant problem relates to the SOG defect density. In particular, the SOG process is susceptible to internal and surface defects in the layer caused by particulate formation and deposition, since IPA dries very quickly compared with other solvents. One method by which particulate formation commonly occurs is the agglomeration of silicon dioxide into particles in the silicon dioxide-IPA mixture itself. The agglomeration results from the existence of the SOG system as a sol-gel, as opposed to a true solution. Another method of particulate formation occurs during the spin application procedure. During application, IPA evaporates rapidly from the mixture upon exposure to air at the tips of the dispense lines that overlie a substrate upon which the integrated circuit devices are to be formed. Particles may thereby encrust the tips. As a result of either method of formation, particles may be deposited as part of the SOG layer. Further, the added complexity of a tri-layer coating process increases the defect density level of SOG layers. However, the tri-layer technique improves over the bi-layer methodology due to the ease of processing the SOG and planarizing layers with a single step through the etching process and with high fidelity.
Another approach to simplify planarizing techniques involves the incorporation of silicon into selected areas of the conventional photoresist. For example, U.S. Pat. No. 4,882,008 relates to a single layer resist process in which the photoresist is processed, e.g., exposed to radiation, and then exposed to a gaseous silicon-containing species such as hexamethyldisilazane. Silicon is thereby incorporated into the exposed regions of the resist. The silicon-enriched resist is then exposed to an oxygen plasma by which the silicon is converted to silicon dioxide.
U.S. Pat. No. 4,963,463 describes a photoresist resin composition based on a radiation-sensitive resin and a photoactive compound that generates an acid upon radiation exposure. The radiation-sensitive resin may be based on a condensate of an alkali-soluble resin such as a novolac with a quinonediazide compound. A substrate coated with the photoresist resin composition is exposed to the appropriate radiation upon which an acid is formed. Thereafter, the coated substrate is treated with a silicon-containing compound, following which silicon is incorporated into the resist layer by reaction with the acid.
Several problems are encountered with some silylated planarizing resists relating to the ability to produce a desired pattern on a substrate. One problem relates to acid generation from a photosensitive precursor. Conversion of such a precursor, for example, by irradiation, can create acid concentration gradients across the planarizing resist layer, particularly at the transitions between positive and negative areas in the resist layer of the irradiated resist. Since uniform patterning in general and formation of uniform and discrete line widths in particular depend on uniform acid concentration in such planarizing resist compositions, acid-generating compositions detract from the desired uniformity and control of the pattern transfer.
A second problem relates to the long-term stability of the resist composition. For certain compositions, e.g., those based on diazonaphthoquinone resists and sensitizers, the presence of even small amounts (e.g., less than 1 wt %) of acid can cause decomposition over time, reducing shelf-life.
Thus, an object of the invention is to provide a highly precise, multi-layer semiconductor manufacturing process having a simplified methodology. A further object of the invention is to simplify the well-known tri-layer processing techniques without sacrificing process resolution.
Another object of the invention is the provision of a process which is relatively free from defect generation in the photoresist materials.
An additional object of the present invention is to provide a stable planarizing resin composition that enhances line width uniformity and overall pattern sharpness.